Gate Driver | richardcrispo

Research Project:

Programming an FPGA with Verilog Code to Implement IGBT Gate Drivers

Contributed to the Oregon State University's Grid Tied Inverter (GTI) Project by developing gate drivers for the power transistors. The GTI uses twelve sets of Insulated Gate Bipolar Transistor (IGBT) pairs as switching power poles to implement both DC/DC converters and DC/AC inverters for three-phase power applications. Developed Verilog code that describes the implementation of transistors in a Field Gate Programmable Array (FPGA) to generate the gate driver signals. An important feature of the driver is that it is required to provide "deadtime" which ensures that there is a small period of time when both the upper and lower IGBT in a half-bridge pair are both off during a switching transition.

In this system a microcontroller computes the Pulse Width Modulation (PWM) data and sends the duty ratio values, along with configuration and control information, to the FPGA. The FPGA inputs this data from the microcontroller and output the IGBT gate drivers. My task was to design the FPGA.

The I/O specification of the FPGA is illustrated in block diagram form in Fig. 1.

Figure 1. The I/O specification of the FPGA. This circuit inputs Data, Address and Control bits aysynchronously from the microcontroller, synchronizes the data to its internal clock and outputs the upper and lower IGBT gate driver signals.

Developed code with the FPGA vendor's development tools and a third-party vendor demonstration board. Used the sawtooth waveform illustration in Fig. 2 to help visualize the development of a PWM algorithm and generate pseudo-code.

Figure 2. The PWM value (green) is compared against the sawtooth waveform (blue) to generate the gate signals (magenta and yellow).

Created Verilog code that implements programmable registers that allow the microcontroller code to:

Set the PWM frequency (while output is disabled)
Program the length of deadtime (while output is disabled)
Update the duty ratio (continually)

Also created a Verilog "stimulus" module that emulates the microcontroller sending various values of address, data and control information to set the internal registers and test the PWM code. This is illustrated in Fig. 3.

Figure 3. The stimulus module generates inputs to the PWM module.

Verified that the PWM module responded appropriately under various test conditions. The oscilloscope screenshot in Fig. 4 shows the FPGA output pins when the stimulus set configures a 5 kHz PWM frequency, a 75% duty ratio and a 50-cycle deadtime (which at a 10 MHz clock equals 5 usec).

Figure 4. The hardware testing results show that the upper gate signal (turquoise) and lower gate signal (yellow) switch at a 5 kHz PWM frequency. Also visually evident is the deadtime when both gates turn off during a switching transition.

Created code to synchronize the data from the microcontroller first before using it to set registers in the PWM algorithm. Also, as an added feature, created a way to allow for the activation of multiple gate pairs with synchronized phase shifting to allow for the implemention of an interleaved buck converter.